1. Field of Invention
The present invention relates generally to optical inspection of semiconductor substrates during the production of semiconductor devices. In particular, the present invention relates to methods and apparatus for detecting the overlay deviation between two patterned layers on a semiconductor substrate.
2. Description of Related Art
One of the most critical process control techniques used in the manufacturing of integrated circuits is the measurement of overlay accuracy between patterned layers, i.e., the measurement of how accurately a patterned layer aligns with respect to another patterned layer located (directly or indirectly) above or below that layer.
Overlay measurement typically is performed on a patterned resist layer prior to etching that layer. If a substrate contains layers that are out of alignment, then the substrate should be reworked (i.e., the photoresist layer(s) are stripped) and returned to the photolithography process to be exposed again at a corrected alignment. Typically, the overlay error is measured, and then the results of the measurement are fed back into the control system that controls the alignment of layers.
Measurement patterns, formed in each of the patterned layers, are used to measure the overlay deviation. The most commonly used measurement patterns are squares, generally referred to as “bar-in-bar” marks, an example of which is shown in FIG. 2A. An outer bar mark 51 is printed on a process layer (lower layer) with side-to-side dimensions of approximately 30 micrometers, and an inner bar mark 52 is printed 6n a photoresist layer (upper layer) with a side-to-side dimension of approximately 15 micrometers. The outer bar mark 51 and the inner bar mark 52 are detected by a microscope system having a CCD camera, for example.
The overlay deviation of the photoresist layer in terms of the process layer is a positional deviation between the outer bar mark 51 and the inner bar mark 52. Hereafter, the overlay deviation will be referred to as an “overlay-offset.” FIG. 2B illustrates a CCD output signal waveform taken along the line 53 shown in FIG. 2A. A signal 54L, a signal 54R, a signal 55L and a signal 55R correspond to the signals emitted from points 51L, 51R, 52L and 52R, respectively. A median point 54C is calculated from the signals 54L and 54R. Similarly, a median point 55C is calculated from the signals 55L and 55R. The overlay-offset in the X-direction is determined by calculating the difference between the median point 54C and the median point 55C. This same method is used to determine the overlay-offset in the Y-direction. A zero overlay-offset at all alignment marks on the substrate (the substrate can be, for example, a silicon wafer, a glass or quartz substrate, or a substrate made from semiconductor materials other than silicon) means that the photoresist layer is exactly aligned with the (underlying) process layer. In this case, the substrate is forwarded to the next manufacturing process without any reworking being done.
However, even if the measured overlay-offset is 0, a displacement error between the two layers may exist. Generally, there are two reasons for this (unmeasured) displacement error. The two reasons are tool induced shift (TIS) and wafer induced shift (WIS), to be explained below.
Tool induced shift is an error in the measurement which is caused by the tool which performs the measurement. The tool includes the CCD, the optical system of the tool (which includes the illumination system for illuminating the substrate and the detection system optics by which the image of the substrate is observed by the CCD), and software that is used to control the system. TIS can be caused, for example, when the illumination light is not telecentric or when an optical axis of the illumination system and/or of the detection optical system is not exactly perpendicular to the substrate. TIS can be calculated by the following equation (1):TIS=(M(0)+M(180))/2   Equation (1)in which M(0) is the overlay-offset calculated at a 0° orientation of the alignment mark, and M(180) is the overlay-offset calculated when the substrate is rotated by 180° (known as the 180° orientation of the alignment mark). In FIG. 2A, the sheet surface is defined as an X-Y plane, and an axis perpendicular to the sheet is defined as the Z-axis. The overlay-offset is measured at θ=0° orientation of the substrate, and then the substrate (including the bar-in-bar mark) is rotated by θ=180° about the Z-axis so that overlay-offset at θ=180° can be measured. Thus, M(0) and M(180) can be measured in order to determine TIS. In order to minimize the displacement error, TIS should be compensated. An overall TIS corrected value (referred to as TCV (TIS corrected value)) is used as an overlay-offset value for an evaluation of the alignment. The following equation (2) shows how TCV is calculated:TCV=M(0)−TIS=(M(0)−M(180))/2   Equation (2)
Wafer induced shift (i.e., errors in the measurement results due to wafer induced shift) occurs due to characteristics of the patterned layers formed on the substrate. One cause of WIS is an asymmetric (non-uniform) processing that is performed on the film layers formed on the substrate. For example, if a step that removes or polishes part of a layer from the substrate, or if a step that deposits a layer onto the substrate, is not performed uniformly over the entire substrate, it may cause WIS. For example, certain layers are made very thin by performing a chemical mechanical planarization (CMP) process on that layer in order to remove a part of the thickness of the layer. This CMP process typically is performed using a rotating disk that is contacted with the uppermost layer on the substrate in order to remove part of that layer. Since the speed of the disk at its outer perimeter is higher than the speed of the disk near its center, different effects can be caused on the substrate layer near the outer perimeter of the disk compared to the inner (center) portion of the disk. For example, the directions of throughholes can be become tilted (in the direction in which the disk rotates) as one progresses from the center of the substrate toward the outer perimeter thereof. In addition, during deposition, typically a source of the deposited material is located above the substrate at the location of the central axis of the substrate. The vaporized particles to be deposited on the substrate are emitted from this point source, and can become deposited unequally between the center and outer perimeter of the substrate. These asymmetric processing steps can cause WIS errors in the measurements made during the overlay measurement process. WIS should be compensated for as well as TIS. However, WIS compensation is very difficult and therefore is not done very frequently, as described below.
Typically substrates are processed in batches (also called “lots”) corresponding to the number of substrates that can be held in a cassette. A typical cassette capacity is 25 substrates. Overlay inspection typically is performed on three wafers from each lot. Thus, if a lot includes 25 substrates, the overlay inspection (including TIS evaluation) is conducted on, for example, the first, tenth and twentieth substrates of the lot. However, in order to measure WIS, a process referred to as after etching inspection (AEI) is performed. AEI is time consuming and involves viewing the substrate using, for example, a scanning electron microscope (SEM). AEI, however, damages the circuitry formed on the substrate, such that the measured substrate must be reworked. AEI is not a regular procedure, and therefore typically is conducted once per day or once per week or once per month. It is not practical to perform AEI on each lot of substrates.
Thus, WIS is not regularly evaluated. Solving issues related to WIS is more important than ever because, with increasingly smaller circuit patterns, process control technologies (such as overlay accuracy) become more and more critical. The required precision specification for overlay machines is about 2.5 nm for 70 nm technology node. Currently, the precision of overlay measurement, which defines measurement repeatability, is 1 nm or less for the actual process substrate. The precision performance is sufficient for the current overlay specification requirements. On the other hand, the accuracy performance, i.e., how close the measurement is to a true overlay-offset without WIS compensation, is still over 5-10 nm. Therefore, it is desirable to measure WIS and compensate WIS values for the measured overlay-offset values, in order to improve. Thus, as noted above, WIS is periodically measured and compensated for. It would, however, be desirable to evaluate WIS more frequently without requiring frequent performance of AEI.